HT80C51 User Manual
Peripheral Modules – Serial Peripheral Interface (SPI)
Handshake Solutions
© Philips Electronics N.V. 2005
Page 75 of 132
SPR1
SPR0
Baud rate
0
0
fspi_clk_i / 1
0
1
fspi_clk_i / 2
1
0
fspi_clk_i / 8
1
1
fspi_clk_i / 16
SPSR
SPI status register
addr = F6H
reset value = 00H
bits
7
6
5
4
3
2
1
0
SPIF
WCOL
0
0
0
0
0
0
bit
Symbol
Function
SPSR.7
SPIF
1:
0:
SPI data complete flag
SPIF is set upon completion of a data transfer. If SPIF =1 and SFR bit
SPIE (SPCR.7) is set, an SPI interrupt is generated.
While SPIF is 1, any write attempts to SPDR are inhibitted until SPDR is
read.
SPIF has to be cleared by software by reading SPSR first and accessing
SPDR afterwards.
SPSR.6
WCOL
1:
0:
Write collision flag
set by hardware, when SPDR is written while a data transfer is in pro-
gress
cleared by hardware, when first SPSR is read and then SPDR is ac-
cessed.
SPSR.5
SPSR.4
SPSR.3
SPSR.2
SPSR.1
SPSR.0
reserved bits
write always 0, read 0
SPDR
SPI data register
addr = F7H
reset value = 00H
bits
7
6
5
4
3
2
1
0
SPDR
bit
Symbol
Function
SPDR.7
..
SPDR.0
Data to transmit or received by the SPI interface.
The data register SPDR is used to communicate transmit and receive data between the
controller and the SPI. Transmit data is provided by writing to this register and receive
data can be read from this register. Only a write to this register will initiate transmis-
sion/reception of another byte, and this will only occur in the master device. At the com-
pletion of transmitting a byte of data, the SPIF status bit is set in both the master and the
slave devices.
When the controller reads SPDR, a buffer is actually read. The corresponding SPIF must
be cleared by the time a second transfer of data from the shift register to the read buffer
is initiated or an overrun condition will exist. In cases of overrun, the byte that causes the
overrun is lost.
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