Handshake Solutions
HT80C51 User Manual
Peripheral Modules – I2C Interface (SIO1)
Page 56 of 132
© Philips Electronics N.V. 2005
switches to the defined “not addressed” Slave Receiver mode. The STO flag is auto-
matically cleared by hardware.
If the STA and STO bits are both set, the a STOP condition is transmitted to the I2C
bus if SIO1 is in a Master mode (in a Slave mode, SIO1 generates an internal STOP
condition which is not transmitted). SIO1 then transmits a START condition.
STO = “0”:
When the STO bit is reset, no STOP condition will be generated.
The Serial Interrupt Flag, SI
SI = “1”:
When the SI flag is set, then, if the EA and ES1 (interrupt enable register) bits are also
set, a serial interrupt is requested. SI is set by hardware when one of 25 of the 26
possible SIO1 states is entered. The only state that does not cause SI to be set is
state F8H, which indicates that no relevant state information is available.
While SI is set, the low period of the serial clock on the SCL line is stretched, and the
serial transfer is suspended. A high level on the SCL line is unaffected by the serial in-
terrupt flag. SI must be reset by software.
SI = “0”:
When the SI flag is reset, no serial interrupt is requested, and there is no stretching of
the serial clock on the SCL line.
The Assert Acknowledge Flag, AA
AA = “1”:
If the AA flag is set, an acknowledge (low level to SDA) will be returned during the
acknowledge clock pulse on the SCL line when:
-
The “own slave address” has been received
-
The general call address has been received while the general call bit (GC) in
S1ADR is set
-
A data byte has been received while SIO1 is in the Master Receiver mode
-
A data byte has been received while SIO1 is in the addressed Slave Receiver
mode
AA = “0”:
if the AA flag is reset, a not acknowledge (high level to SDA) will be returned during
the acknowledge clock pulse on SCL when:
-
A data has been received while SIO1 is in the Master Receiver mode
-
A data byte has been received while SIO1 is in the addressed Slave Receiver
mode
When SIO1 is in the addressed Slave Transmitter mode, state C8H will be entered after the last serial
is transmitted (see [Figure 11]).
When SI is cleared, SIO1 leaves state C8H, enters the not addressed Slave Receiver mode, and the
SDA line remains at a high level. In state C8H, the
AA flag can be set again for future address recogni-
tion.
When SIO1 is in the not addressed Slave mode, its own slave address and the general call address
are ignored. Consequently, no acknowledge is returned, and a serial interrupt is not requested. Thus,
SIO1 can be temporarily released from the I2C bus while the bus status is monitored. While SIO1 is
released from the bus, START and STOP conditions are detected, and serial data is shifted in. Ad-
dress recognition can be resumed at any time by setting the AA flag. If the AA flag is set when the
part’s own Slave address or the general call address has been partly received, the address will be
recognized at the end of the byte transmission.
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