Handshake Solutions
HT80C51 User Manual
Peripheral Modules – Timers 0 and 1
Page 28 of 132
© Philips Electronics N.V. 2005
5.2.3.
Interrupts
Each of the timers can generate two separate interrupt signals, which are directly connected to inter-
rupt request lines of the interrupt controller. The following table and [Figure 8] describe these sources
and connections. For interrupt priorities and interrupt vectors see the description of the interrupt con-
troller.
interrupt
source
Description
Interrupt
signal
timer 0:
IE0
Set by hardware when external interrupt t01_int0_n_i is detected. If SFR
bit IT0 is set, the flag is set on a falling edge of the external interrupt, if IT0 is
cleared, a low level on the external interrupt line cause an interrupt.
Cleared when interrupt is processed.
int0
TF0
Timer 0 overflow flag.
Set by hardware on Timer/Counter overflow.
Cleared by hardware when processor vectors to interrupt routine, or clearing
the bit in software.
int1
timer 1:
IE1
Set by hardware when external interrupt t01_int1_n_i is detected. If SFR
bit IT1 is set, the flag is set on a falling edge of the external interrupt, if IT1 is
cleared, a low level on the external interrupt line cause an interrupt.
Cleared when interrupt is processed.
int2
TF1
Timer 1 overflow flag.
Set by hardware on Timer/Counter overflow.
Cleared by hardware when processor vectors to interrupt routine, or clearing
the bit in software.
int3
IE1
t01_int1_n_i
IT1
0
1
IE0
t01_int0_n_i
IT0
0
1
TF0
TF1
int0
int1
int2
int3
[Figure 8]
Interrupt Sources From the Timers 0 and 1
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