HT80C51 datasheet(76/132 Pages) ETC2

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Handshake Solutions

HT80C51 User Manual

Peripheral Modules – Serial Peripheral Interface (SPI)

Page 76 of 132

A write to SPDR is not buffered; the data is directly stored into the shift register for trans-

mission.

5.6.3.

Interrupts

When a data transfer is completed, bit SPIF (SPSR.7) is set. If SPIF =1 and SFR bit SPIE (SPCR.7) is set,

an SPI interrupt on interrupt line int6 is generated.

SPIF has to be cleared by software by reading SPSR first and accessing SPDR afterwards.

5.6.4.

Operation

[Figure 28] shows a block diagram of the serial peripheral interface circuitry. When a master device

transmits data to a slave device via the MOSI line, the slave device responds by sending data to the

master device via the master’s MISO line. This implies full duplex transmission with both data out and

data in synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte

received and eliminates the need for separate transmit-empty and receiver-full status bits. A single

status bit (SPIF) is used to signify that the l/O operation has been completed.

The SPI is double buffered on read, but not on write. If a write is performed during data transfer, the

transfer occurs uninterrupted, and the write will be unsuccessful. This condition will cause the write

collision (WCOL) status bit in the SPSR to be set. After a data byte is shifted, the SPIF flag of the SPSR is

set.

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