48 / 132 page
Handshake Solutions
HT80C51 User Manual
Peripheral Modules – I2C Interface (SIO1)
Page 48 of 132
© Philips Electronics N.V. 2005
OTHER DEVICE WITH
I2C INTERFACE
OTHER DEVICE WITH
I2C INTERFACE
P89C66x
P1.7/SDA
P1.6/SCL
SDA
SCL
Rp
Rp
VDD
I2C bus
[Figure 14] Typical I
2C Bus Configuration
12
7
8
ACK
91
2
3-8
ACK
9
REPEATED IF MORE BYTES
ARE TRANSFERRED
CLOCK LINE HELD LOW WHILE
INTERRUPTS ARE SERVICED
ACKNOWLEDGMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGMENT
SIGNAL FROM RECEIVER
R/W
DIRECTION
BIT
SLAVE ADDRESS
MSB
SDA
SCL
STOP
CONDITION
REPEATED
START
CONDITION
P/S
S
START
CONDITION
[Figure 15] Data Transfer on the I
2C Bus
5.5.4.2.
SIO1 Implementation and Operation
[Figure 16] shows how the on-chip I2C bus interface is implemented, and the following text describes
the individual blocks.
Input Filters and Output Stages
The input filters should have I2C compatible input levels. If the input voltage is less than 1.5 V, the
input logic level is interpreted as 0; if the input voltage is greater than 3.0 V, the input logic level is
interpreted as 1. For low speed implementations it is advisable to use input filter circuits for the pins
SDA and SCL, to suppress noise on these signals.
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