HC705MC4GRSSLASHD datasheet(126/180 Pages) NXP

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Serial Communications Interface

MC68HC705MC4 — Rev. 2.0

Serial Communications Interface

11.5.2.1 Character Length

The receiver can accommodate either 8-bit or 9-bit data. The state of the

M bit in SCI control register 1 (SCCR1) determines character length.

When receiving 9-bit data, bit R8 in SCCR1 is the ninth bit (bit 8).

11.5.2.2 Character Reception

During reception, the receive shift register shifts characters in from the

PB5/RDI (receive data input) pin. The SCI data register (SCDR) is the

read-only buffer between the internal data bus and the receive shift

After a complete character shifts into the receive shift register, the data

portion of the character is transferred to the SCDR, setting the receive

data register full (RDRF) flag. The RDRF flag can be used to generate

an interrupt.

11.5.2.3 Receiver Wakeup

So that the MCU can ignore transmissions intended only for other

receivers in multiple-receiver systems, the MCU can be put into a

standby state. Setting the receiver wakeup enable (RWU) bit in SCI

control register 2 (SCCR2) puts the MCU into a standby state during

which receiver interrupts are disabled.

Either of two conditions on the PB5/RDI pin can bring the MCU out of the

standby state:

•

Idle input line condition — If the PB5/RDI pin is at logic 1 long

enough for 10 or 11 logic 1s to shift into the receive shift register,

receiver interrupts are again enabled.

•

Address mark — If a logic 1 occurs in the most significant bit

position of a received character, receiver interrupts are again

enabled.

The state of the WAKE bit in SCCR1 determines which of the two

conditions wakes up the MCU.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D датащи(PDF) 126 Page - NXP Semiconductors