HC705MC4GRSSLASHD datasheet(62/180 Pages) NXP

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Operating Modes

MC68HC705MC4 — Rev. 2.0

Operating Modes

6.6 WAIT Instruction

The WAIT instruction places the MCU in a low-power mode. In wait

mode, the bus clock is halted, suspending all processor and internal bus

activity but the timer. COP, ADC, PWM, and SCI subsystems remain

active. To save more power, the user may optionally disable each

individual subsystem through software before entering wait mode.

Execution of the WAIT instruction automatically clears the I bit in the

condition code register, enabling the IRQ external interrupt. All other

registers, memory, and input/output lines remain in their previous state

unless modified by an active peripheral.

If the 16-bit timer interrupt is enabled, it will cause the processor to exit

wait mode and resume normal operation. The 16-bit timer may be used

to generate a periodic exit from wait mode. The wait mode may also be

exited when an IRQ external interrupt, SCI interrupt, or RESET occurs.

6.7 COP Watchdog Timer Considerations

The COP watchdog timer is active in single-chip mode when selected by

mask option. The COP watchdog timer should be disabled for

applications that will use the wait mode with time periods that will exceed

the COP timeout period.

COP watchdog timer interactions are summarized in Table 6-3.

Table 6-3. COP Watchdog Timer Recommendations

IF the following conditions exist

during WAIT period:

THEN the COP watchdog timer

should be:

WAIT period

less than COP time-out

Enable or disable COP via Mask Option

WAIT period

more than COP time-out

Disable COP via Mask Option

any length WAIT period

Disable COP via Mask Option

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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