HC705MC4GRSSLASHD datasheet(69/180 Pages) NXP

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Input/Output Ports

I/O Port Programming

General Release Specification

Input/Output Ports

7.8 I/O Port Programming

Each pin on ports A–C may be programmed as an input or an output

under software control as shown in Table 7-1, Table 7-2, and Table 7-3.

Port D6 may be programmed as an input or an output and port D7 may

be used as an input only as shown in Table 7-4. The direction of a pin is

determined by the state of its corresponding bit in the associated port

data direction register (DDR). A pin is configured as an output if its

corresponding DDR bit is set to a logic 1. A pin is configured as an input

if its corresponding DDR bit is cleared to a logic 0.

At power-on or reset, all DDRs are cleared, which configures all port pins

as inputs. The DDRs are capable of being written to or read by the

processor. During the programmed output state, a read of the data

level on the I/O port pin.

Table 7-1. Port A I/O Functions

DDRA

I/O Pin Mode

Accesses

to DDRA

@ $0004

Accesses

to Data Register

@ $0000

Read/Write

Read

Write

IN, Hi-Z

DDRA0–DDRA7

PA0–PA7

OUT

DDRA0–DDRA7

PA0–PA7

* Does not affect input, but stored to data register

Table 7-2. Port B I/O Functions

DDRB

I/O Pin Mode

Accesses

to DDRA

@ $0005

Accesses

to Data Register

@ $0001

Read/Write

Read

Write

IN, Hi-Z

DDRB4–DDRB7

PB4–PB7

OUT

DDRB4–DDRB7

PB4–PB7

* Does not affect input, but stored to data register

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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