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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HC705MC4GRS/D датащи(PDF) 77 Page - NXP Semiconductors |
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HC705MC4GRS/D датащи(HTML) 77 Page - NXP Semiconductors |
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77 / 180 page  Analog Subsystem A/D Data Register General Release Specification Analog Subsystem 8.7 A/D Data Register One 8-bit result register is provided. This register is updated each time COCO is set. Reset has no effect on this register. 8.8 A/D During Wait Mode The A/D continues normal operation during wait mode. To decrease power consumption during wait, it is recommended that both the ADON and ADRC bits in the A/D status and control register be cleared if the A/D converter is not being used. If the A/D converter is in use and the system clock rate is above 1.0 MHz, it is recommended that the ADRC bit be cleared. Address: $0024 Bit 7 654321 Bit 0 Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Write: Reset: Unaffected by Reset Figure 8-3. A/D Converter Data Register (ADDR) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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