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HC705MC4GRS/D датащи(PDF) 64 Page - NXP Semiconductors

номер детали HC705MC4GRS/D
подробное описание детали  General Release Specification
PDF  180 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

HC705MC4GRS/D датащи(HTML) 64 Page - NXP Semiconductors

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Input/Output Ports
MC68HC705MC4 — Rev. 2.0
Input/Output Ports
7.3 Port A
Port A is an 8-bit bidirectional port that shares PA1–PA6 with the pulse
width modulator (PWM) subsystem. (See Figure 7-1.) The port A data
register is located at address $0000 and its data direction register (DDR)
is located at address $0004. Reset does not affect the data registers, but
clears the DDRs, thereby setting all of the port pins to input mode.
Writing a 1 to a DDR bit sets the corresponding port pin to output mode.
PA1–PA6 may be used for general I/O applications when the PWM
subsystem is disabled. PA0–PA7 feature larger P-channel output
devices and are capable of sourcing more current than a standard port
(refer to Section 14. Electrical Specifications).
Figure 7-1. Port A I/O Circuitry
READ $0000
WRITE $0000
READ $0004
DATA
REGISTER BIT
I/O
PIN
OUTPUT
INTERNAL HC05
DATA BUS
RESET
(RST)
WRITE $0004
DATA DIRECTION
REGISTER BIT
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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