HC705MC4GRSSLASHD datasheet(83/180 Pages) NXP

номер детали	HC705MC4GRS/D

подробное описание детали	General Release Specification

PDF	180 Pages

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производитель	NXP [NXP Semiconductors]

домашняя страница	http://www.nxp.com

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16-Bit Timer

Timer

General Release Specification

16-Bit Timer

The timer registers and alternate counter registers can be read at any

time without affecting their values. However, the alternate counter

registers differ from the timer registers in one respect: a read of the timer

alternate counter registers can be read at any time without the possibility

of missing timer overflow interrupts due to clearing of the TOF. See

Figure 9-4.

The free-running counter is initialized to $FFFC during reset and is a

read-only register.

Figure 9-4. State Timing Diagram for Timer Overflow

$FFFF

$0001

$0002

$0000

INTERNAL

TIMER

T00

T01

T10

T11









OVERFLOW

16-BIT

FLAG (TOF)

BUS CLOCK

CLOCKS

COUNTER

NOTE:

The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by read-

ing the timer status register (TSR) during the high portion of the internal clock followed by reading the

LSB of the counter register pair (TMRL).

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D датащи(PDF) 83 Page - NXP Semiconductors