HC705MC4GRSSLASHD datasheet(100/180 Pages) NXP

100 / 180 page

Pulse Width Modulator

MC68HC705MC4 — Rev. 2.0

Pulse Width Modulator

Mask Enable (MEx)

When set, MEx enables the output mask feature of the PWMx

subsystem. When enabled, all three pins of a channel will be used for

subsystem output, that is the port registers will have no effect. All

unselected pins (pins that have their corresponding CSx bit clear) will

output the corresponding value of the MSKx bit. All selected pins (pins

that have their corresponding CSx bit set) will output the PWM

waveform. See Table 10-1.

The mask feature allows the user to drive any of the PWM subsystem

ports (PA1–PA6) to a logic 1 or logic 0 synchronous with the register

interlock timing. All PWM outputs can therefore be modified

simultaneously to either drive PWM, logic 1, or logic 0 signals.

When MEx is clear, output mask feature is disabled and the port will

function as a normal I/O port if the CSx bit is cleared. This feature

allows some of the ports to be freed up for normal I/O when not used

for PWM output. If the corresponding CSx bit is set, the selected

channel will output the PWM waveform.

Polarity (POLx)

The polarity bit initializes the PWM output to a logic 1 or logic 0 at the

start of each PWM cycle. See Figure 10-5 and Figure 10-6.

1 = Initialize output to one. Toggles to zero at data PWMx match.

0 = Initialize output to zero. Toggles to one at data PWMx match.

Figure 10-5. PWM Waveforms (POLx = 1)

PWM DATA REGISTER = $00

PWM DATA REGISTER VALUE

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D датащи(PDF) 100 Page - NXP Semiconductors