HC705MC4GRSSLASHD datasheet(29/180 Pages) NXP

номер детали	HC705MC4GRS/D

подробное описание детали	General Release Specification

PDF	180 Pages

Scroll/Zoom	100%

производитель	NXP [NXP Semiconductors]

домашняя страница	http://www.nxp.com

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Memory

Bootstrap Mode Memory Map

General Release Specification

Memory

2.4 Bootstrap Mode Memory Map

Memory space is identical to the user mode, as shown in Figure 2-1.

2.5 I/O and Control Registers

Figure 2-3, Figure 2-4, and Figure 2-5 briefly describe the I/O and

control registers according to their locations ($0000–$002F) as shown in

Figure 2-2. Reading unimplemented bits will return unknown states, and

writing unimplemented bits will be ignored.

Port A Data Register

$0000

Port B Data Register

$0001

Port C Data Register

$0002

Port D Data Register

$0003

Port A Data Direction Register

$0004

Port B Data Direction Register

$0005

Port C Data Direction Register

$0006

Port D Data Direction Register

$0007

Core Timer Control & Status Register

$0008

Core Timer Counter Register

$0009

SCI Baud Rate Register

$000A

SCI Control Register 1

$000B

SCI Control Register 2

$000C

SCI Status Register

$000D

SCI Data Register

$000E

IRQ Status and Control Register

$000F

PWMA-D Data Direct Register

$0010

PWMA-I Data Interlock Register

$0011

PWMB-D Data Direct Register

$0012

Figure 2-2. I/O and Control Registers

Memory Map

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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