HC705MC4GRSSLASHD datasheet(42/180 Pages) NXP

42 / 180 page

Interrupts

MC68HC705MC4 — Rev. 2.0

Interrupts

4.3 Reset Interrupt Sequence

The reset function is not in the strictest sense an interrupt; however, it is

acted upon in a similar manner as shown in Figure 4-1. A low level input

on the RESET pin or internally generated RST signal causes the

program to vector to its starting address which is specified by the

contents of memory locations $0FFE and $0FFF. The I bit in the

condition code register (CCR) is also set. The MCU is configured to a

known state during this type of reset, as described in Section 5. Resets.

4.4 Software Interrupt

The software interrupt (SWI) is an executable instruction. It is also a

nonmaskable interrupt since it is executed regardless of the state of the

I bit in the CCR. As with any instruction, interrupts pending during the

previous instruction will be serviced before the SWI opcode is fetched.

The interrupt service routine address for the SWI instruction is specified

by the contents of memory locations $0FFC and $0FFD.

4.5 Hardware Interrupts

All hardware interrupts are maskable by the I bit in the CCR. If the I bit

is set, all hardware interrupts (internal and external) are disabled.

Clearing the I bit enables the hardware interrupts. Four hardware

interrupts are explained in the following sections.

4.5.1 External Interrupt

If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts

(internal and external) are disabled. Clearing the I bit enables interrupts

(subject to their individual interrupt enable control flag status). External

interrupt (IRQ) now has an independent interrupt mask bit in the IRQ

status and control register (ISCR) that also must be cleared to enable its

corresponding interrupt.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D датащи(PDF) 42 Page - NXP Semiconductors