HC705MC4GRSSLASHD datasheet(90/180 Pages) NXP

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16-Bit Timer

MC68HC705MC4 — Rev. 2.0

16-Bit Timer

9.6 Timer Control Register

The timer control (TCR) and free-running counter (TMRH, TMRL,

ACRH, ACRL) registers are the only registers of the 16-bit timer affected

by reset. The output compare port (TCMP) is forced low after reset and

remains low until OLVL is set and a valid output compare occurs.

ICIE2 — Input Capture Interrupt Enable 2

Bit 7, when set, enables input capture 2 interrupts to the CPU. The

interrupt will occur at the same time bit 7 (ICF2) in the TSR register is

set.

ICIE1 — Input Capture Interrupt Enable 1

Bit 6, when set, enables input capture 1 interrupts to the CPU if and

only if the TCMP/TCAP1 bit (bit 3) is cleared. The interrupt will occur

at the same time bit 6 (ICF1) in the TSR register is set. If the

TCMP/TCAP1 bit is set, the input capture 1 interrupt is disabled,

regardless of the state of the ICIE1 bit.

TOIE — Timer Overflow Interrupt Enable

Bit 5, when set, enables timer overflow (rollover) interrupts to the

CPU. The interrupt will occur at the same time bit 5 (TOF) in the TSR

OCIE — Output Compare Interrupt Enable

Bit 4, when set, enables output compare interrupts to the CPU if and

only if the TCMP/TCAP1 bit (bit 3) is set. The interrupt will occur at the

same time bit 4 (OCF) in the TSR register is set. If the TCMP/TCAP1

bit is cleared, the output compare interrupt is disabled, regardless of

the state of the OCIE bit.

Address:

$0017

Bit 7

654321

Bit 0

Read:

ICIE2

ICIE1

TOIE

OCIE

TCMP/

TCAP1

IEDG1

IEDG2

OLVL

Write:

Reset:

00000

= Unimplemented

U= Unaffected

Figure 9-11. Timer Control Register (TCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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