HC705MC4GRSSLASHD datasheet(130/180 Pages) NXP

номер детали	HC705MC4GRS/D

подробное описание детали	General Release Specification

PDF	180 Pages

Scroll/Zoom	100%

производитель	NXP [NXP Semiconductors]

домашняя страница	http://www.nxp.com

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Serial Communications Interface

MC68HC705MC4 — Rev. 2.0

Serial Communications Interface

WAKE — Wakeup Bit

This read/write bit determines which condition wakes up the SCI: a

logic 1 (address mark) in the most significant bit position of a received

character or an idle condition of the PD5/RDI pin. Reset has no effect

on the WAKE bit.

1 = Address mark wakeup

0 = Idle line wakeup

11.6.3 SCI Control Register 2

SCI control register 2 has the following functions:

•

Enables the SCI receiver and SCI receiver interrupts

•

Enables the SCI transmitter and SCI transmitter interrupts

•

Enables SCI receiver idle interrupts

•

Enables SCI transmission complete interrupts

•

Enables SCI wakeup

•

Transmits SCI break characters

TIE — Transmit Interrupt Enable

This read/write bit enables SCI interrupt requests when the TDRE bit

becomes set. Reset clears the TIE bit.

1 = TDRE interrupt requests enabled

0 = TDRE interrupt requests disabled

Address:

$000C

Bit 7

654321

Bit 0

Read:

TIE

TCIE

RIE

ILIE

RWU

SBK

Write:

Reset:

00000000

Figure 11-6. SCI Control Register 2 (SCCR2)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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