HC705MC4GRSSLASHD datasheet(96/180 Pages) NXP

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Pulse Width Modulator

MC68HC705MC4 — Rev. 2.0

Pulse Width Modulator

10.2 Introduction

The pulse width modulator (PWM) subsystem has two 8-bit channels

(PWMA and PWMB). The PWM has a programmable prescaler, divide

by 1.5 added to the initial prescaler, polarity, and mux enable with

channel masking for motor control applications. The PWM is capable of

generating signals from 0% to 100% duty cycle. A $00 in either PWM

data register yields an OFF output (0%) with the polarity control bit set

to one for that channel (for example, PWMA or PWMB), but a $FF yields

a duty of 255/256. To achieve the 100% duty (ON output), the polarity

control bit is set to zero for that channel (for example, PWMA or PWMB)

while the data register has $00.

NOTE:

The symbol 'x’ is used in this section to indicate either channel A or

channel B. For example, PWMx refers to either PWMA or PWMB.

10.3 PWM Registers

The PWM subsystem is controlled through four control registers: CTL-A,

CTL-B, RATE, and UPDATE. CTL-A, CTL-B, and the data registers

feature a write interlock and buffer mechanism to permit their contents

to be updated simultaneously, preventing undesirable glitching of the

associated port A output. The CTL-A and CTL-B registers contain bits to

control the PWM subsystem outputs on PA1–PA6 (PWM, logic 0 or logic

1) and PWM polarity bits.

The PWM subsystem control and data registers are all buffered, as

shown in Figure 10-2. Each register consists of an active register, which

contains the data used by the PWM subsystem, and a buffer register,

which contains the data most recently written to the register address.

Writes to the buffer registers are transferred to the active registers at the

end of the PWM period if the respective bit in the UPDATE register is set

to 0. If it is set to 1, the transfer will occur immediately. In addition, when

the respective update bit is clear, a predefined sequence of register

accesses may also need to be completed before the new contents of

these registers are transferred. This sequence of accesses is referred to

as a register interlock mechanism and is intended to allow more than

one register to be modified before effecting the PWM operation. The

Freescale Semiconductor, Inc.

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