HC705MC4GRSSLASHD datasheet(51/180 Pages) NXP

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Resets

Internal Resets

General Release Specification

Resets

5.4.1 Illegal Address Reset

When an opcode fetch occurs at an address that is not in the RAM or

ROM/EPROM, the part automatically resets. The part will also reset

when an opcode fetch inadvertently occurs at an address within the

bootstrap ROM while the device is in user mode.

5.4.2 Power-On Reset

An internal reset is generated on power-up to allow the internal clock

generator to stabilize. The power-on reset is strictly for power turn-on

conditions and should not be used to detect a drop in the power supply

voltage. There is a 4064 internal processor clock cycle (tcyc) oscillator

stabilization delay after the oscillator becomes active. If the RESET pin

is active at the end of this 4064-cycle delay, the MCU will remain in the

reset condition until RESET goes inactive.

The POR will generate the RST signal and reset the MCU. If any other

reset function is active at the end of this 4064-internal clock cycle delay,

the RST signal will remain active until the other reset condition(s) end.

During POR, RESET will be driven low for four cycles. Although the

external reset pulse is short, it is recommended that the user tie RESET

to VDD through a 1 kΩ resistor (not directly).

5.4.3 Computer Operating Properly Reset

When the COP watchdog timer is enabled (by mask option), the internal

COP reset is generated automatically by a time-out of the COP

watchdog timer. This timer is implemented as part of the core timer. See

Section 12. Core Timer. The COP watchdog counter is cleared by

writing a logical 0 to bit 0 at location $0FF0.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D датащи(PDF) 51 Page - NXP Semiconductors