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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HC705MC4GRS/D датащи(PDF) 54 Page - NXP Semiconductors |
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HC705MC4GRS/D датащи(HTML) 54 Page - NXP Semiconductors |
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54 / 180 page  Operating Modes MC68HC705MC4 — Rev. 2.0 Operating Modes The conditions required to enter each mode are shown in Table 6-1. The mode of operation is determined by: 1. The voltages on the IRQ and PD7/TCAP2 pins on the rising edge of the external RESET pin. 2. The subsequent rising edge of RESET after an internal reset pulls the RESET pin low. 6.3 User Mode The user mode allows the MCU to function as a self-contained microcontroller, with maximum use of the pins for on-chip peripheral functions. All address and data activity occurs within the MCU and are not available externally. User mode is entered on the rising edge of RESET if the IRQ pin is within the normal operating voltage range. In the user mode, port A shares six of its eight input/output (I/O) lines with the dual channel pulse-width modulator (PWM) subsystem. Port B shares two of its four I/O lines with the serial communications interface (SCI) subsystem. Port C shares all of its 8-bit I/O lines with the analog-to-digital (A/D) subsystem. Port D shares its two port lines with the 16-bit timer subsystem. The pinout for user mode is shown in Figure 1-2 and Figure 1-3. Table 6-1. Operating Mode Conditions after Reset RESET Pin IRQ/VPP PD7/TCAP2 Mode VSS to VDD VSS to VDD User VPP VDD Bootloader Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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