HC705MC4GRSSLASHD datasheet(92/180 Pages) NXP

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16-Bit Timer

MC68HC705MC4 — Rev. 2.0

16-Bit Timer

9.7 Timer Status Register

Reading the timer status register (TSR) satisfies the first condition

required to clear status flags and interrupts. The only remaining step is

to read (or write) the register associated with the active status flag

(and/or interrupt). This method does not present any problems for input

capture or output compare functions.

However, a problem can occur when using a timer interrupt function and

reading the free-running counter at random times to, for example,

measure an elapsed time. If the proper precautions are not designed into

the application software, a timer overflow flag (TOF) could

unintentionally be cleared if:

1. The TSR is read when bit 5 (TOF) is set, and

2. The LSB of the free-running counter is read, but not for the

purpose of servicing the flag or interrupt.

The alternate counter registers (ACRH, ACRL) contain the same values

as the timer registers (TMRH, TMRL). Registers ACRH and ACRL can

be read at any time without affecting the timer overflow flag (TOF) or

interrupt.

ICF2 — Input Capture 1 Flag

Bit 7 is set when the edge specified by IEDG2 in register TCR has

been sensed by the input capture edge detector fed by pin TCAP2.

This flag, and the input capture interrupt, can be cleared by reading

pair (ICRL2).

Address:

$0018

Bit 7

654321

Bit 0

Read:

ICF2

ICF1

TOF

OCF

0000

Write:

Reset:

UUUU

0000

= Unimplemented

U = Unaffected

Figure 9-12. Timer Status Register (TSR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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