HC705MC4GRSSLASHD datasheet(55/180 Pages) NXP

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Operating Modes

Bootloader Mode

General Release Specification

Operating Modes

6.4 Bootloader Mode

Bootloader mode is entered upon the rising edge of RESET if the

IRQ/VPP pin is at VPP and the PD7/TCAP2 pin is at logic 1. The

bootloader code resides in ROM between $0F01 and $0FEF. This

program handles copying of user code from an external EPROM or host

computer into the on-chip EPROM. Figure 6-1 shows the timing

required to interface the device being programmed to a host. The

bootloader performs one programming pass at t

EPGM per byte. When

programming is complete, the bootloader code then performs a verify

pass.

NOTE:

The external user code addresses must correspond directly with the

internal EPROM addresses.

6.4.1 Bootloader Functions

Two pins are used to select various bootloader functions. These pins are

PC2 and PC3. In addition, PC1 must be connected to VSS. PC0 is a

SYNC pin, which is used to synchronize the MCU to an off-chip source

driving data to be programmed into the MCU as shown in Figure 6-1.

Two other pins, PC6 and PC7 are used to drive the PROG LED and the

VERF LED respectively. The PC2 and PC3 configurations required to

enter the programming modes are shown in Table 6-1.

NOTE:

PC0 must be connected to VSS through a resistor.

Table 6-2. Bootloader Functions

PC2

PC3

Mode

Program/Verify

Verify Only

Dump EPROM

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D датащи(PDF) 55 Page - NXP Semiconductors