HC705MC4GRSSLASHD datasheet(25/180 Pages) NXP

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General Description

Functional Pin Description

General Release Specification

General Description

1.5.3 RESET

Driving this input low will reset the MCU to a known startup state. This

pin is pulled low by internal resets. The RESET pin contains an internal

Schmitt trigger to improve its noise immunity. Refer to Section 5.

Resets.

1.5.4 PA0, PA1/PWMA1, PA2/PWMB1, PA3/PWMA2, PA4/PWMB2, PA5/PWMA3,

PA6/PWMB3, and PA7

These eight I/O pins comprise port A and are shared with the PWM

subsystem. The state of any pin is software programmable and all port

A lines are configured as inputs during power-on or reset. All port A pins

have high source current capability to simplify interfacing to external

devices, such as small triacs. Refer to Section 7. Input/Output Ports

and Section 10. Pulse Width Modulator.

1.5.5 PB4/TDO, PB5/RDI, PB6, and PB7

These four I/O pins comprise port B. Two pins are shared with the SCI

communication subsystem. The state of any pin is software

programmable and all port B lines are configured as inputs during

power-on or reset. Refer to Section 7. Input/Output Ports and Section

11. Serial Communications Interface.

1.5.6 PC0:5/AD0:5, PC6/VREFH, and PC7/VREFL

These eight I/O pins comprise port C and are shared with the A/D

converter subsystem. The state of any pin is software programmable

and all port C lines are configured as inputs during power-on or reset.

Refer to Section 7. Input/Output Ports and Section 8. Analog

Subsystem.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D датащи(PDF) 25 Page - NXP Semiconductors