HC705MC4GRSSLASHD datasheet(46/180 Pages) NXP

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Interrupts

MC68HC705MC4 — Rev. 2.0

Interrupts

4.5.2 Timer Interrupts

The following paragraphs describe the timer interrupts.

4.5.2.1 Input Capture Interrupts

The input capture interrupts are generated by the 16-bit timer as

described in Section 9. 16-Bit Timer. The input capture interrupt flags

are located in the timer status register (TSR) and the corresponding

enable bits can be found in the timer control register (TCR). The interrupt

service routine addresses are specified by the contents of memory

locations $0FF8 and $0FF9 for input capture 2 and by the contents of

memory locations $0FF6 and $0FF7 for input capture 1.

4.5.2.2 Output Compare Interrupt

The output compare interrupt is generated by the 16-bit timer, as

described in Section 9. 16-Bit Timer. The output compare interrupt flag

is located in register TSR and its corresponding enable bit can be found

in register TCR. The interrupt service routine address is specified by the

contents of memory locations $0FF4 and $0FF5.

NOTE:

The output compare interrupt is not available when the TCMP/TCAP1

timer channel is configured for input capture. See 9.4 Output Compare.

4.5.2.3 Timer Overflow Interrupt

The timer overflow interrupt is generated by the 16-bit timer as described

in Section 9. 16-Bit Timer. The timer overflow interrupt flag is located in

TCR. The I bit in the CCR must be clear for the timer overflow interrupt

to be enabled. This internal interrupt will vector to the interrupt service

routine located at the address specified by the contents of memory

locations $0FF4 and $0FF5. The timer overflow and the output compare

function share the same interrupt vector, thus requiring the user to poll

interrupt request flags.

Freescale Semiconductor, Inc.

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