HC705MC4GRSSLASHD datasheet(44/180 Pages) NXP

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Interrupts

MC68HC705MC4 — Rev. 2.0

Interrupts

IRQM — IRQ Enable Mask

The IRQM bit is a read/write bit that will disable the IRQ interrupt when

set. IRQM is cleared by reset.

1 = IRQ interrupt request disabled

0 = IRQ interrupt request enabled

IRQS — IRQ Sensitivity

The IRQS bit is a read/write bit that will select whether the IRQ

interrupt is edge-sensitive only or both edge-sensitive and

level-sensitive. IRQS is cleared by reset.

1 = Both edge-sensitive and level-sensitive

0 = Edge-sensitive only

EDGE — IRQ Active Edge Select

The EDGE bit is a read/write bit that allows the user to select which

edge, rising or falling, of the signal at the IRQ pin will generate an

interrupt. Both rising and falling edge sensitivity may be achieved in

software by toggling the EDGE bit from within the IRQ service routine.

EDGE is cleared by reset.

1 = Rising edge IRQ interrupt

0 = Falling edge IRQ interrupt

REQ — IRQ Interrupt Request

The REQ bit is a read-only bit. The IRQ interrupt request bit and latch

are cleared during IRQ exception processing. Therefore, one external

IRQ interrupt pulse can be latched and subsequently serviced as

soon as the I bit is cleared. REQ will be cleared by reset.

1 = IRQ interrupt request pending

0 = No IRQ interrupt request pending

Address:

$000F

Bit 7

654321

Bit 0

Read:

IRQM

IRQS

EDGE

REQ

Write:

ACK

Reset:

00000000

= Unimplemented

Figure 4-2. IRQ Status and Control Register (ISCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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