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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HC705MC4GRS/D датащи(PDF) 41 Page - NXP Semiconductors |
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HC705MC4GRS/D датащи(HTML) 41 Page - NXP Semiconductors |
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41 / 180 page  Interrupts Introduction General Release Specification Interrupts instruction that was to be executed when the interrupt took place. Figure 4-1 shows the sequence of events that occur during interrupt processing. The interrupts fall into three categories: reset, software, and hardware. Figure 4-1. Interrupt Processing Flowchart IS I BIT SET? FROM RESET LOAD PC FROM: SWI: $0FFC, $0FFD IRQ: $0FFA-$0FFB ICF2: $0FF8-$0FF9 ICF1: $0FF6-$0FF7 OCF/TOF: $0FF4-$0FF5 SCI: $0FF2-$0FF3 CTOF/RTIF: $0FF0-$0FF1 SET I BIT IN CCR. STACK PC, X, A, CC. CLEAR IRQ REQUEST LATCH. RESTORE REGISTERS FROM STACK CC, A, X, PC. Y N EXECUTE INSTRUCTION. FETCH NEXT INSTRUCTION. IRQ INTERRUPT? Y N TIMER INTERRUPT? Y N SWI INSTRUCTION? Y N RTI INSTRUCTION? Y N SCI INTERRUPT? Y N CORE TIMER INTERRUPT? Y N Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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