HC705MC4GRSSLASHD datasheet(68/180 Pages) NXP

номер детали	HC705MC4GRS/D

подробное описание детали	General Release Specification

PDF	180 Pages

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производитель	NXP [NXP Semiconductors]

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Input/Output Ports

MC68HC705MC4 — Rev. 2.0

Input/Output Ports

7.7 Port D

Port D is a 2-bit port. PD7 and PD6 are shared with the 16-bit timer. PD6

is a bidirectional I/O pin but PD7 is an input-only pin. The port D data

is located at address $0007. Reset clears the DDR, setting PD6 to an

input but does not affect the data registers. (See Figure 7-5.)

PD6 may be used for general I/O applications when the timer subsystem

is disabled. PD7 may be used as a general-purpose input when the timer

subsystem is disabled. When the timer subsystem is enabled, port D

registers are still accessible to software. Writing to either of the port D

registers with the timer enabled could interfere with timer operation. See

Section 9. 16-Bit Timer for a discussion of the timer subsystem.

Figure 7-5. Port D Circuitry

READ $0003

TCMP

READ $0007

DATA

I/O

OUTPUT

INTERNAL HC05

DATA BUS

RESET

(RST)

TCMP/TCAP1

DATA DIRECTION

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D датащи(PDF) 68 Page - NXP Semiconductors