HC705MC4GRSSLASHD datasheet(113/180 Pages) NXP

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Pulse Width Modulator

PWM Operation in User Mode

General Release Specification

Pulse Width Modulator

10.7.2 Operation with the Same PWM Rates

If RA equals RB, channel A and channel B are assumed to be operating

together in a synchronous fashion and are interlocked. This interlock

mechanism is in addition to the buffering and the PWM data/control

interlock described in 10.7.1 Interlock Operation.

A write to either PWMB data register must be followed by a write to either

PWMA data register. Any new data written will become effective at the

end of the current PWM cycle during which the write to PWMA took place

as shown in Figure 10-16. The interlocking between the data registers

is disabled when the channels have different periods.

A write to CTL-B control register must be followed by a write to the

CTL-A control register. Any new data written to either register will

become effective at the end of the current PWM cycle during which the

write to CTL-A took place. The interlocking between the control registers

is disabled when the channels have different periods.

Writing to the PWMx-I interlock address will also activate the interlock

mechanism with the CTL-x register as described in 10.7.1 Interlock

Operation. The two interlocking mechanisms, channel A/channel B and

data/control, may be in effect at the same time.

Example 1

Writing to PWMB-I ($13) will require a write to CTL-B ($15) to satisfy

the data/control interlock. In addition, if RA = RB, the write to either

PWMB data register will require a write to either PWMA data register,

and the write to CTL-B control register will require a write to CTL-A

contents of all these registers will be transferred into their respective

active registers at the end of the current PWM cycle during which all

invoked interlock mechanisms become satisfied if the UPDATE A and

UPDATE B bits are clear. For either channel, if the corresponding

update bit is set, the transfer for that channel will occur immediately

after the interlock mechanism is satisfied.

Freescale Semiconductor, Inc.

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