HC705MC4GRSSLASHD datasheet(111/180 Pages) NXP

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Pulse Width Modulator

PWM Operation in User Mode

General Release Specification

Pulse Width Modulator

10.7 PWM Operation in User Mode

The following subsections describe the PWM operation in user mode.

10.7.1 Interlock Operation

All PWM registers are buffered. The register buffering prevents data

written to either the control or data registers from affecting the PWM

cycle under way at the time of the data write. The interlock mechanism

extends this principle to multiple registers by preventing data written to

groups of data and/or control registers from affecting the PWM

configuration currently active until all writes are complete. There are

several interlock options from which the user can pick depending upon

the change of function desired. The register interlock mechanism

operation is shown in Figure 10-16.

Writing to a PWMx interlock address will activate a data/control interlock

mechanism with the corresponding CTL-x register. Under such a

condition, the new value written to the PWM interlock data register will

not be effective until the end of the current PWM cycle during which a

write to the corresponding control register was executed.

A typical application for such a mechanism is to generate 100% duty

cycle when not using the PWM output mask feature (MEx = 0).

Synchronized changes to both data and control registers are, therefore,

necessary to avoid PWM glitches. 100% duty cycle can be generated by

clearing PWMx-I, then toggling the state of the POLx bit in the

corresponding CTL-x register. Any new data written to either register will

become effective at the end of the current PWM cycle during which the

write to CTL-x took place.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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