HC705MC4GRSSLASHD datasheet(116/180 Pages) NXP

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Pulse Width Modulator

MC68HC705MC4 — Rev. 2.0

Pulse Width Modulator

PWM channel A is configured such that the PWM signal may be directed

to either PA1 (CSA1 = 1) or PA3 (CSA2 = 1). When not driving the PWM

signal, these ports should drive a logic 0 (MEA = 1, MSKA1 = 0,

CSA1 = 0, MSKA2 = 0, CSA2 = 0). PA5 drives either a logic 0 (MEA = 1,

MSKA3 = 0, CSA3 = 0) or logic 1 (MEA = 1, MSKA3 = 1, CSA3 = 0).

PA7 is configured as an output port (DDRA7 = 1). The software

moderates the PWM output pulse width based on speed feedback data

obtained from a tachometer or other such device. The tachometer

typically would drive an input capture, providing data to the MCU from

which velocity and acceleration information can be derived. The system

could be modified to provide positional data for servo applications. The

motor direction is determined by the current direction through it. Forward

rotation requires Q4 (PA7) and Q2 (PA3) enabled. Reverse rotation

requires Q3 (PA5) and Q1 (PA1) enabled.

The truth table shown in Table 10-4 defines the H-bridge drive

requirements for the motor from which the software would select based

upon other system inputs.

The MC68HC705MC4 can be configured to drive two motors using both

PWM channels.

Table 10-4. Brushed DC Motor Truth Table

Function

Forward

Off

PWM

Off

Reverse

PWM

Off

Stop

Off

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D датащи(PDF) 116 Page - NXP Semiconductors