BLUENRG-2 datasheet(126/190 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-2

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DocID030675 Rev 2

In Mode 1a, Timer/Counter 2 (TnCNT2) behaves differently from the way it behaves in

modes 1 to 4. If an underflow condition occurs, the counter is preset to 0x0000 and not

0xFFFF.

The Timer/Counter 1 starts to count:



either on an external event on TnB input,



or by software if TnPTSE bit has been set by setting the TnPTET bit.

The start of count request through TnPTET bit setting when software trigger

option is chosen must be done after the MFT is enabled (TnEN bit in TnMCTRL

Any time the counter is stopped by choosing "no-clock" by the Timer/Counter 1 clock

selector (TnCKC register), it will obtain its first reload value after it has been started again

from the TnCRB register. Upon Reset, the MFT is disabled. Every time this mode is

entered, the first reload in this mode will be from register TnCRB. Once the underflow

condition for TnCNT2 has been reached, TnCNT2 must be initialized again by the

application. It is not reloaded by any reload register.

Timer/Counter 2 can be configured to generate an interrupt upon underflow if enabled by

the TnDIEN bit.

In pulse-train mode, the value of TnCNT2 specifies the number of pulses to be generated,

plus one additional pulse (TnCTN2+1 number of pulses).

In pulse-train mode, the trigger logic uses events on TnB to enable the Timer/Counter 1

clock. This function has to be enabled by setting the TnPTSTE bit to 0.

TnB can be configured to sense either positive-going or negative-going transitions.

Timer/Counter 1 can be configured to toggle the TnA output bit upon underflow. This

results in the generation of a pulse signal on TnA, with the width and duty cycle controlled

by the values stored in the TnCRB and TnCRB registers. This is a processor-independent

PWM signal because once the timer is set up, no more interaction is required from the

software or the CPU in order to generate one or more PWM signal pulses. The initial value

of the PWM output signal can be selected by software to be either high or low.

The timer can be configured to generate separate interrupts upon reload from TnCRB and

TnCRB. The TnAPND or TnBPND flags, which are set by the hardware upon occurrence of

a timer reload, indicate which interrupt has occurred. The interrupts can be enabled or

disabled under software control.

3.13.2.3

MFT mode 2: dual-input capture mode

The Mode2 is used to capture transitions on two selected input pads of the device. The

Timer/Counter1 can be used to manage the dual-capture feature as follows:



A transition on input pad connected to TnA pin of the MFT generates a transfer of

TnCNT1 register value in TnCRB register.



A transition on input pad connected to TnB pin of the MFT generates a transfer of

TnCNT1 register value in TnCRB register.

The Timer/Counter2 can be used:



As a system counter: to count down at the rate of the selected clock.

Note: the device input pad selection is done using MFTX_IOSEL register.

The transition edge to capture has to be defined in TnAEDG and TnBEDG bits of the

TnMCTRL register.

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