BLUENRG-2 datasheet(74/190 Pages) STMICROELECTRONICS

74 / 190 page

Functional details

BlueNRG-2

74/190

DocID030675 Rev 2

The received status (parity, framing and break error) of Xon/Xoff characters does

not have to be valid for these characters to be accepted as valid matches.

When the software transmit flow control is enabled through the SFTMOD bit field in the

UART_XFCR register, the transmitter will automatically insert an Xoff character if the

received FIFO has passed the received trigger level (bit field RXIFLSEL in the UART_IFLS

signal the remote transfer was stopped. When the receive FIFO falls below the trigger

level, Xon character is automatically inserted in the transmission stream and the RTXDIS

bit in the UART_FR register is cleared.

Table 76: Control bits to enable and program transmit software flow control

SFSEN

SFTMOD

Function

xxb

Software flow control disabled.

00b

Software transmit flow control disabled.

01b

Use Xon1, Xoff1 for matching.

10b

Use Xon2, Xoff2 for matching.

11b

Use Xon1 and Xon2, Xoff1 and Xoff2 for matching.

After an Xoff character has been transmitted, if the software flow controlled is

turned off, a Xon character will automatically be inserted in the transmission

stream and the bit RTXDIS bit in the UART_FR register is cleared.

Transmission of an Xon/Xoff character follows the standard transmission protocol

as programmed in the transmitter registers (word length, parity and so on).

When using the software transmit flow control, there are some cautions to take to

manage the interrupt handler. The software must react on RX interrupt (the flag

will be raised once the RX FIFO contains the RXIFSEL trigger level. Then the

interrupt handler must first poll the UART_FR.RTXDIS bit until it is set to indicate

the Xoff byte transmission is over and only then read the RX FIFO content. Note

that hardware and software flow control cannot be enabled simultaneously.

Software transmit flow control

When the special character detection feature is enabled through the SPECHAR bit in the

UART_XFCR register, the software flow control is turned off and the receiver compares

received characters with the Xoff2 value. When a match is found, the interrupt bit XOFFRIS

in the raw interrupt register UART_RIS is set. If the corresponding interrupt mask bit is set,

the UART interrupt pin is asserted. The transmission is not halted. The special character is

written into the received FIFO. The interrupt bit XOFFIS will be cleared when the

corresponding bit in interrupt clear register is written as 1b.

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