BLUENRG-2 datasheet(73/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

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filled up to the watermark level. When the receive FIFO watermark level is reached, the

UART_RTS signal is de-asserted, indicating that there is no more room to receive any

more data. The transmission of data is expected to cease after the current character has

been transmitted. The UART_RTS signal is reasserted when data has been read out of the

receive FIFO so that it is filled to less than the watermark level. If RTS flow control is

disabled and the UART is still enabled, then data is received until the receive FIFO is full,

or no more data is transmitted to it.

If CTS flow control is enabled, then the transmitter checks the UART_CTS signal before

transmitting the next byte. If the UART_CTS signal is asserted, it transmits the byte

otherwise, transmission does not occur. The data continues to be transmitted while

UART_CTS is asserted, and the transmit FIFO is not empty. If the transmit FIFO is empty

and the UART_CTS signal is asserted no data is transmitted. If the UART_CTS signal is

de-asserted and CTS flow control is enabled, then the current character transmission is

completed before stopping. If CTS flow control is disabled and the UART is enabled, then

the data continues to be transmitted until the transmit FIFO is empty.

3.9.2.4

Software flow control

Software flow control is enabled through register UART_XFCR bit SFEN.

Software receive flow control

Once the software receive flow control is enabled, the receiver compares the incoming data

with the programmed Xoff values. Different combinations of software receive flow control,

which can be selected through SFRMOD, where only 1 character match is needed or in

which 2 Xoff characters must be received sequentially.

Table 75: Control bits to enable and program receive software flow control

SFSEN

SFRMOD

Function

xxb

Software flow control disabled.

00b

Software receive flow control disabled.

01b

Use Xon1, Xoff1 for matching.

10b

Use Xon2, Xoff2 for matching.

11b

Use Xon1 & Xon2, Xoff1 & Xoff2 for matching.

If received characters match the programmed Xoff values, the transmission will stop as

soon as the current character is completely transferred. The interrupt bit XOFFRIS in the

raw interrupt register UART_RIS is set. If the corresponding interrupt mask bit is set, the

corresponding bit in the UART_MIS register is set and the UART interrupt pin is asserted.

Following such a transmission suspension, the receiver will monitor incoming characters for

a match with the programmed Xon values. The matching strategy is programmable through

SWRFCPROG in register UART_XFCR. Once a match is found, the receiver clears the

interrupt bit XOFFRIS in the raw interrupt register UART_RIS and the Xoff interrupt is

disabled. The transmission can then resume normally. When the XONANY bit in register

UART_XFCR is set, any incoming character is accepted as a valid Xon condition and the

transmission can then resume. The received character is written into the received FIFO.

If the software flow control is enabled, the received Xon/Xoff characters are never

written into the received FIFO. Exceptions to this occur when the special

character detection feature is enabled (Xoff2 is then written into FIFO upon a

special character match) and when the Xon-any bit is set.

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