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BLUENRG-2 датащи(PDF) 64 Page - STMicroelectronics |
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BLUENRG-2 датащи(HTML) 64 Page - STMicroelectronics |
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64 / 190 page ![]() Functional details BlueNRG-2 64/190 DocID030675 Rev 2 Bit Field name Reset RW Description 3 SOD 0x0 RW Slave mode output disable (slave mode only). 0: SPI can drive the MISO signal in slave mode. 1: SPI must not drive the MISO signal in slave mode. In multiple slave system, it is possible for a SPI master to broadcast a message to all slaves in the system while ensuring only one slave drives data onto the serial output line MISO. 5:4 RENDN 0x0 RW Receive endian format. 00b: The element is received MSByte-first and MSbit-first. 01b: The element is received LSByte-first and MSbit-first. 10b: The element is received MSByte-first and LSbit-first. 11b: The element is received LSByte-first and LSbit-first. The cases 00b and 11b are set for data frame size from 4 to 32 bits. The cases 01b and 10b are set only for data frame size 16, 24 and 32 bits. 6 MWAIT 0x0 RW MicroWire wait state bit enable: 0: No wait state 1: One wait state 9:7 RXIFLSEL 0x0 RW Receive interrupt FIFO level select. This bit field selects the trigger points to receive FIFO interrupt: 000b: RX FIFO contains 1 element or more. 001b: RX FIFO contains 4 elements or more. 010b: RX FIFO contains 8 elements or more. Others: Reserved. 12:10 TXIFLSEL 0x0 RW Transmit interrupt FIFO level select. This bit field selects the trigger points to transmit FIFO interrupt: 000b: TX FIFO contains 1 element or more. 001b: TX FIFO contains 4 elements or more. 010b: TX FIFO contains 8 elements or more. Others: Reserved. 13 RESERVED 0x0 R RESERVED 17:14 MSPIWAIT 0x0 RW Motorola SPI Wait mode. This value is used to insert a wait state between frames. 19:18 TENDN 0x0 RW Transmit endian format. 00b: The element is transmitted MSByte-first and MSbit-first. 01b: The element is transmitted LSByte-first and MSbit-first. 10b: The element is transmitted MSByte-first and LSbit-first. 11b: The element is transmitted LSByte-first and LSbit-first. The cases 00b and 11b are set for data frame size from 4 to 32 bits. The cases 01b and 10b are set only for data frame size 16, 24 and 32 bits. 20 RESERVED 0x0 R RESERVED 21 DATAINDEL 0x0 RW Data input delay. 0: No delay is inserted in data input. 1: A delay of 2 clock cycles is inserted in the data input path. 31:22 RESERVED 0x0 R RESERVED |
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