BLUENRG-2 datasheet(79/190 Pages) STMICROELECTRONICS

79 / 190 page

BlueNRG-2

Functional details

DocID030675 Rev 2

79/190

Bit

Field name

Reset

Description

0x0

Overrun error. This bit is set to 1 if data is received and the

receive FIFO is already full. This is cleared to 0 by a write to

ECR (data value is not important). The FIFO contents remain

valid since no further data is written when the FIFO is full, only

the content of the shift register are overwritten. The CPU or

DMA must now read the data in order to empty the FIFO.

31:4

RESERVED

0x0

RESERVED

Table 80: UART - TIMEOUT register description: address offset UART_BASE_ADDR+0x0C

Bit

Field name

Reset

Description

21:0

PERIOD

0x1FF

Timeout period configuration. This bit field contains the

timeout period for the UART timeout interrupt assertion. The

receive timeout interrupt is asserted when the receive FIFO is

not empty and no further data is received over a programmed

timeout period. The duration before the timeout interrupt will

assert is calculated by the following formula:

timeout = PERIOD / (OverSamplingFactor * BaudRate) Where

OverSamplingFactor is:

16 if OVSFACT is 0

8 if OVSFACT is 1.

31:22

RESERVED

0x0

RESERVED

Table 81: UART - FR register description: address offset UART_BASE_ADDR+0x18

Bit

Field name

Reset

Description

CTS

0x0

Clear to send.

2:1

RESERVED

0x0

RESERVED

BUSY

0x0

UART Busy. If this bit is set to 1, the UART is busy

transmitting data. This bit remains set until the complete byte,

including all the stop bits, has been sent from the shift register.

However, if the transmit section of the UART is disabled in the

middle of a transmission, the BUSY bit gets cleared. This bit is

set again once the transmit section is re-enabled to complete

the remaining transmission.This bit is set as soon as the

transmit FIFO becomes nonempty (regardless of whether the

UART is enabled or not).

RXFE

0x1

Receive FIFO empty. If the FIFO is disabled (bit FEN = 0b),

this bit is set when the receive holding register is empty. If the

FIFO is enabled (FEN = 1b), the RXFE bit is set when the

receive FIFO is empty.

TXFF

0x0

Transmit FIFO full. If the FIFO is disabled (bit FEN = 0b), this

bit is set when the transmit holding register is full. If the FIFO

is enabled (FEN = 1b), the TXFF bit is set when the transmit

FIFO is full.

RXFF

0x0

Receive FIFO full. If the FIFO is disabled (bit FEN = 0b), this

bit is set when the receive holding register is full. If the FIFO is

enabled (FEN = 1b), the RXFF bit is set when the receive

FIFO is full.

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