BLUENRG-2 datasheet(65/190 Pages) STMICROELECTRONICS

65 / 190 page

BlueNRG-2

Functional details

DocID030675 Rev 2

65/190

Table 58: SPI - DR register description: address offset SPI_BASE_ADDR+0x08

Bit

Field

name

Reset

Description

31:0

DATA

0x0

Transmit/Receive data:

Read: RX FIFO is read.

Write: TX FIFO is written.

Data must be right-justified when a data size of less than 32-bit is

programmed. Unused bits are ignored by the transmit logic. The

receive logic automatically right-justifies data.

Table 59: SPI - SR register description: address offset SPI_BASE_ADDR+0x0C

Bit

Field name

Reset

Description

TFE

0x1

Transmit FIFO empty:

0: TX FIFO is not empty.

1: TX FIFO is empty.

TNF

0x1

Transmit FIFO not full:

0: TX FIFO is full.

1: TX FIFO is not full.

RNE

0x0

Receive FIFO not empty:

0: RX FIFO is empty.

1: RX FIFO is not empty.

RFF

0x0

Receive FIFO full:

0: RX FIFO is not full.

1: RX FIFO is full.

BSY

0x0

SPI busy flag:

0: SPI is idle.

1: SPI is currently transmitting and/or receiving a frame or the

TX FIFO is not empty.

31:5

RESERVED

0x0

RESERVED

Table 60: SPI - CPSR register description: address offset SPI_BASE_ADDR+0x10

Bit

Field name

Reset

Description

7:0

CPSDVSR

0x0

Clock prescaler divisor. It must be an even number from 2 to

254. The value is used to generate the transmit and receive bit

rate of the SPI. The bit rate is:

FSSPCLK / [CPSDVR x (1+SCR)]

where SCR is a value from 0 to 255, programmed through the

SSP_CR0 register.

31:8

RESERVED

0x0

RESERVED

Table 61: SPI - IMSC register description. Address offset SPI_BASE_ADDR+0x14.

Bit

Field name

Reset

Description

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