BLUENRG-2 datasheet(95/190 Pages) STMICROELECTRONICS

95 / 190 page

BlueNRG-2

Functional details

DocID030675 Rev 2

95/190

Bit

Field name

Reset

Description

21:15

RESERVED

0x0

RESERVED

31:16

SLSU

0xF

Slave data setup time. SLSU defines the data setup time after

SCL clock stretching in terms of i2c_clk cycles. Data setup

time is actually equal to SLSU-1 clock cycles. The typical

values for i2c_clk of 16 MHz are SLSU = 5 in standard mode

and SLSU = 3 in fast modes.

Table 101: I2C2 - MCR register description: address offset I2CX_BASE_ADDR+0x0C

Bit

Field name

Reset

Description

0x0

Operation

0: Indicates a master write operation.

1: Indicates a master read operation.

7:1

0x0

Address. Includes the 7-bit address or the LSB bits of the10-

bit address used to initiate the current transaction

10:8

EA10

0x0

Extended address. Includes the extension (MSB bits) of the

field A7 used to initiate the current transaction

0x0

Start byte:

0: The start byte procedure is not applied to the current

transaction.

1: The start byte procedure is prefixed to the current

transaction.

13:12

0x0

Address type:

00b: The transaction is initiated by a general call command. In

this case the fields OP, A7, EA10 are "don't care".

01b: The transaction is initiated by the 7-bit address included

in the A7 field.

10b: The transaction is initiated by the 10-bit address included

in the EA10 and A7 fields.

0x0

Stop condition:

0: The current transaction is not terminated by a STOP

condition. A repeated START condition is generated on the

next operation which is required to avoid to stall the I²C line.

1: The current transaction is terminated by a STOP condition.

25:15

LENGTH

0x0

Transaction length. Defines the length, in terms of the number

of bytes to be transmitted (MW) or received (MR). In case of

write operation, the payload is stored in the Tx FIFO. A

transaction can be larger than the Tx FIFO size. In case of

read operation the length refers to the number of bytes to be

received before generating a not-acknowledge response. A

transaction can be larger than the Rx FIFO size. The I²C clock

line is stretched low until the data in Rx FIFO are consumed.

31:26

RESERVED

0x0

RESERVED

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