BLUENRG-2 datasheet(48/190 Pages) STMICROELECTRONICS

48 / 190 page

Functional details

BlueNRG-2

48/190

DocID030675 Rev 2

Bit

Field name

Reset

Description

HTIF2

0x0

Channel 2 half transfer flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 2.

1: A half transfer (HT) event occurred on channel 2.

TEIF2

0x0

Channel 2 transfer error flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 2.

1: A transfer error (TE) occurred on channel 2.

GIF3

0x0

Channel 3 global interrupt flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 3.

1: A TE, HT or TC event occurred on channel 3.

TCIF3

0x0

Channel 3 transfer complete flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 3.

1: A transfer complete (TC) occurred on channel 3.

HTIF3

0x0

Channel 3 half transfer flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 3.

1: A half transfer (HT) event occurred on channel 3.

TEIF3

0x0

Channel 3 transfer error flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 3.

1: A transfer error (TE) occurred on channel 3.

GIF4

0x0

Channel 4 global interrupt flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 4.

1: A TE, HT or TC event occurred on channel 4.

TCIF4

0x0

Channel 4 transfer complete flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 4.

1: A transfer complete (TC) occurred on channel 4.

HTIF4

0x0

Channel 4 half transfer flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 4.

1: A half transfer (HT) event occurred on channel 4.

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