BLUENRG-2 datasheet(91/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

DocID030675 Rev 2

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3.10.2.3

I²C configuration

Following a Reset, the I²C logic is disabled and must be configured when in this state.

The control register (CR) and baud rate register (BRCR) need to be programmed to

configure the following parameters of the peripheral:



Master or slave.



7- or 10-bit addressing mode



Speed mode



Clock rate

If in slave mode, the SCR register has to be programmed with the selected slave

address.

Then, if in master mode, the MCR register is used to define the transaction:



Read or write.



Slave addresses (7- or 10-bit) to communicate with.



Addressing a 7- or 10-bit slave address.



Stop condition, to generate a stop or restart condition at the end of the transaction (for

consecutive transactions).



Transaction length

For a master write, the data to transmit have to be written to the transmit FIFO in

the I2C_TFR register. For a master read, when the master transaction is done,

data are available in the receive FIFO in I2C_RFR.

3.10.2.4

DMA interface

The I²C controller includes a specific DMA interface. The following section describes the

signals interface, data flow and programming model for the RX and the TX paths.

The DMA interfaces are separated for each path and two DMA request channels shall be

used for a device.

In RX mode, a DMA transfer based on a single descriptor shall be used and the DMA RX

channel must be programmed for a peripheral-to-memory transfer where the flow controller

is the DMA. Each descriptor is related to a single I²C transaction (master read or write-to-

slave operation) and no linked list item should be used. The transfer length shall be

programmed on the DMA and the termination of the frame transfer is notified by the

assertion of the related interrupt I2C_RISR:STD or I2C_RISR:MTD bits. In case of read-

from-slave operation, on the DMA (master device) the transfer length shall be programmed

according to the I2C_MCR:LENGTH register field. In case of write-to-slave operation, on

the DMA (slave device) the maximum length (not the real length because it is unknown)

shall be programmed.

In TX mode, a DMA transfer based on a single descriptor shall be used and the DMA TX

channel must be programmed for a memory-to-peripheral transfer where the flow controller

is the DMA. Each descriptor is related to a single I²C transaction (master write or read-

from-slave operation) and no linked list item should be used. The transfer length shall be

programmed on the DMA and the termination of the frame transfer is notified by the

assertion of the related interrupt I2C_RISR:STD or I2C_RISR:MTD bits. In case of write-to-

slave operation, on the DMA (master device) the transfer length shall be programmed

according to the I2C_MCR:LENGTH register field. In case of read-from-slave operation, on

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