BLUENRG-2 datasheet(70/190 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-2

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DocID030675 Rev 2

Figure 13: UART character frame

The FIFOs can be disabled. In this case, the transmit and receive sides of the UART have

1-byte holding registers (the bottom entry of the FIFOs). The overrun bit is set when a word

has been received, and the previous one was not yet read. In this implementation, the

1-byte register.

3.9.2.2

Baud rate divisor

The baud rate divisor is a 22-bit number consisting of a 16-bit integer (BRDI) and a 6-bit

fractional part (BRDF). The fractional baud rate divider enables the use of any clock to act

as UART_CLK, while it is still possible to generate all the standard baud rates.

The 16-bit integer is loaded through the UART_IBRD register and the 6-bit fractional part is

loaded into the UART_FBRD register. The baud rate divisor has the following relationship:

When bit OVSFACT = 0b: divisor = UARTCLK/(16 x baud rate) = BRDI + BRDF.

When bit OVSFACT = 1b: divisor = UARTCLK/(8 x baud rate) = BRDI + BRDF.

Calculation of the fractional 6-bit number (DIVFRAC) is done by taking the fractional part of

the required baud rate divisor and multiplying it by 64 (that is, 2n, where n is the width of

the UART_FBRD register) and adding 0.5 to account for rounding errors:

DIVFRAC = integer(BRDF * 64 + 0.5)

The maximum deviation error using a 6-bit UART_FBRD register is 1/64 * 100 = 1.56%.

This occurs when DIVFRAC = 1, and the error is cumulative over 64 clock ticks.

Example 1: Calculating the divisor value (with OVSFACT = 0b).

If the required baud rate is 460 800 and the UART clock frequency is 16 MHz then:

Baud rate divisor = (16 x 106) / (16 x 460 800) = 2.170

BRDI = 2 and BRDF = 0.170

Therefore fractional part DIVFRAC = integer(BRDF * 64 + 0.5) = 11

Generated baud rate divider = 2 + (11 / 64) = 2.1718

Generated baud rate = (16 x 106) / (16 x 2.172) = 460 447

Error = (460 800 - 460 405) / 460 800 x 100 = 0.077 %

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