BLUENRG-2 datasheet(123/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

DocID030675 Rev 2

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

Pulse-accumulate mode



External-event mode



Prescaled system clock mode



Slow clock input mode (available only if 32 MHz system clock is used, allows to

divide by 2 and obtains a 16 MHz system clock as clock source).



Two I/O pins (TnA and TnB) with programmable edge detection that operate as:



Capture and preset inputs



External event (clock) inputs



PWM outputs.



Two interrupts, one for each counter, that can be triggered by a:



Timer underflow



Timer reload



Input capture



Pulse train for generation of single or multiple PWM pulses.

3.13.2

MFT functional description

The MFT can be configured in five different modes. At each mode is associated a particular

function for the two timers both for counter and reload registers as reported in Table 156:

"MFT modes".

Table 156: MFT modes

Mode

Description

Timer

Counter 1

(TnCNT1)

Reload / capture A

(TnCRB)

Reload / Capture

B (TnCRB)

Timer

Counter 2

(TnCNT2)

PWM and

system timer or

external event

counter

Counter for

PWM

Auto reload A =

PWM time 1

Auto reload B =

PWM time 2

System time

or external

event

PWM pulse train

Counter for

PWM

Auto reload A =

PWM time 1

Auto reload B=

PWM time 2

Pulse

counter

Dual-input

capture and

system timer

Capture A

and B time

base

Capture

timer/counter 1

value upon TnA

event

Capture

Timer/counter 1

value upon TnB

event

System

timer

Dual

independent

timer

Time base

for first timer

Reload register

fortimer/counter 1

Reload register

for timer/counter 2

Time base

for second

timer

Single-input

capture and

single timer

Time base

for first timer

Reload register

forTimer/Counter 1

Capture

timer/counter 1

value upon TnB

event

Capture B

time base

3.13.2.1

MFT mode 1: processor-independent PWM

In Mode1, the timer counter 1 (TnCNT1) can be used to generate a PWM signal on an

output pin of the device. In this mode, the PWM output can emulate a clock signal with

customized duty-cycle. Indeed, the TnCNT1 is alternatively reloaded by TnCRB and

TnCRB registers. The initial value of the PWM output signal can be selected by software to

be either high or low thanks to the TnAOUT bit in TnMCTRL register. This bit impacts

which reload value, is used for high level and low level of the PWM signal as shown in

Figure 15: "PWM signal" below.

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