BLUENRG-2 datasheet(56/190 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-2

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DocID030675 Rev 2

Bit

Field name

Reset

Description

31:0

0x0

Base address of the peripheral data register from/to

which the data will be read/written. When PSIZE is 01

(16-bit), the PA[0] bit is ignored. Access is

automatically aligned to a halfword address. When

PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is

automatically aligned to a word address.

Table 50: DMA_CHx - CMAR register description: address offset

DMA_CHX_BASE_ADDR+0x0C

Bit

Field name

Reset

Description

31:0

0x0

Base address of the memory area from/to which the

data will be read/written. When MSIZE is 01 (16-bit),

the MA[0] bit is ignored. Access is automatically

aligned to a halfword address. When MSIZE is 10

(32-bit), MA[1:0] are ignored. Access is automatically

aligned to a word address.

3.8

SPI

3.8.1

Introduction

The BlueNRG-2 integrates a serial peripheral interface compatible with the Motorola and

National Semiconductor Microwire standards.

Main features are:



Maximal supported baud rate is 1 MHz in slave mode and 8 MHz in master mode.



Parallel-to-serial conversion on data written to an internal 32-bit wide, 16-location

deep transmitter FIFO.



Serial-to-parallel conversion on received data, buffering in a 32-bit wide 16-location

deep receive FIFO.



Programmable data frame size from 4-bit to 32-bit.



Programmable clock bit rate and prescaler.



Programmable clock phase and polarity in SPI mode.



Support for Direct Memory Access (DMA).

3.8.2

Functional overview

The SPI performs serial-to-parallel conversion on data received from a peripheral device on

the SPI_IN pin, and parallel-to-serial conversion on data written by CPU for transmission

on the SPI_OUT pin.

The role of the SPI pins are defined by the SPI master or SPI slave role.

Table 51: SPI pin assignments

SPI role

SPI_IN pin

SPI_OUT pin

Master

MISO

MOSI

Slave

MOSI

MISO

The transmit and receive paths are buffered with internal FIFO memories allowing up to 16

x 32-bit values to be stored independently in both transmit and receive modes. FIFOs may

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