BLUENRG-2 datasheet(41/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

DocID030675 Rev 2

41/190

Channel configuration procedure

The following sequence should be followed to configure a DMA channelx (where x is the

channel number).

Set the peripheral register address in the DMA_CPARx register. The data will be

moved from/ to this address to/ from the memory after the peripheral event.

Set the memory address in the DMA_CMARx register. The data will be written to or

read from this memory after the peripheral event.

Configure the total number of data to be transferred in the DMA_CNDTRx register.

After each peripheral event, this value will be decremented.

Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register.

Configure data transfer direction, circular mode, peripheral & memory incremented

mode, peripheral & memory data size, and interrupt after half and/or full transfer in the

DMA_CCRx register.

Activate the channel by setting the ENABLE bit in the DMA_CCRx register.

As soon as the channel is enabled, it can serve any DMA request from the peripheral

connected on the channel. Once half of the bytes are transferred, the half-transfer flag

(HTIF) is set and an interrupt is generated if the Half-Transfer Interrupt Enable bit (HTIE) is

set. At the end of the transfer, the Transfer Complete Flag (TCIF) is set and an interrupt is

generated if the Transfer Complete Interrupt Enable bit (TCIE) is set.

Circular mode

Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC

scan mode). This feature can be enabled using the CIRC bit in the DMA_CCRx register.

When circular mode is activated, the number of data to be transferred is automatically

reloaded with the initial value programmed during the channel configuration phase, and the

DMA requests continue to be served.

Memory-to-memory mode

The DMA channels can also work without being triggered by a request from a peripheral.

This mode is called Memory-to-Memory mode. If the MEM2MEM bit in the DMA_CCRx

setting the Enable bit (EN) in the DMA_CCRx register. The transfer stops once the

DMA_CNDTRx register reaches zero. Memory-to-Memory mode may not be used at the

same time as Circular mode.

3.7.2.4

Programmable data width, data alignment and endianness

When PSIZE and MSIZE are not equal, the DMA performs some data alignments as

described in Table 41: "Programmable data width and endian behavior (when bits PINC =

MINC = 1)": Programmable data width & endian behavior (when bits PINC = MINC = 1).

Table 41: Programmable data width and endian behavior (when bits PINC = MINC = 1)

Source

port

width

Destination

port width

Number of

data items

to transfer

(NDT)

Source

content:

address/data

Transfer operations

Destination

content:

address/data

@0x0 / B0

1: READ B0[7:0]

@0x0 then WRITE

B0[7:0] @0x0

@0x0 / B0

@0x1 / B1

2: READ B1[7:0]

@0x1 then WRITE

B0[7:0] @0x1

@0x1 / B1

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