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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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BLUENRG-2 датащи(PDF) 66 Page - STMicroelectronics |
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BLUENRG-2 датащи(HTML) 66 Page - STMicroelectronics |
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66 / 190 page  Functional details BlueNRG-2 66/190 DocID030675 Rev 2 Bit Field name Reset RW Description 0 RORIM 0x0 RW Receive overrun interrupt mask: 0: RX FIFO written to while full condition interrupt is masked (irq disabled). 1: RX FIFO written to while full condition interrupt is not masked (irq enabled). 1 RTIM 0x0 RW Receive timeout interrupt mask: 0: RX FIFO not empty or no read prior to the timeout period interrupt is masked (irq disabled). 1: RX FIFO not empty or no read prior to the timeout period interrupt is not masked (irq enabled). 2 RXIM 0x0 RW Receive FIFO interrupt mask: 0: Receive interrupt is masked (irq disabled). 1: Receive interrupt is not masked (irq enabled). 3 TXIM 0x0 RW Transmit FIFO interrupt mask: 0: Transmit interrupt is masked (irq disabled). 1: Transmit interrupt is not masked (irq enabled). 4 TURIM 0x0 RW Transmit underrun interrupt mask: 0: Transmit underrun interrupt is masked (irq disabled). 1: Transmit underrun interrupt is not masked (irq enabled). 5 TEIM 0x0 RW Transmit FIFO empty interrupt mask: 0: TX FIFO empty interrupt is masked (irq disabled). 1: TX FIFO empty interrupt is not masked (irq enabled). 31:6 RESERVED 0x0 R RESERVED Table 62: SPI - RIS register description: address offset SPI_BASE_ADDR+0x18 Bit Field name Reset RW Description 0 RORRIS 0x0 R Receive overrun raw interrupt status 1 RTRIS 0x0 R Receive time out raw interrupt status 2 RXRIS 0x0 R Receive raw interrupt status 3 TXRIS 0x0 R Transmit raw interrupt status 4 TURRIS 0x0 R Transmit underrun raw interrupt Status 5 TERIS 0x0 R Transmit FIFO Empty Raw Interrupt Status 31:6 RESERVED 0x0 R RESERVED Table 63: SPI - MIS register description: address offset SPI_BASE_ADDR+0x1C Bit Field name Reset RW Description 0 RORMIS 0x0 R Receive Overrun Masked Interrupt Status: gives the interrupt status after masking of the receive overrun interrupt. 1 RTMIS 0x0 R Receive Time Out Masked Interrupt Status: gives the interrupt status after masking of receive timeout interrupt. 2 RXMIS 0x0 R Receive Masked Interrupt Status: gives the interrupt status after masking of the receive interrupt. |
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