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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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BLUENRG-2 датащи(PDF) 72 Page - STMicroelectronics |
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BLUENRG-2 датащи(HTML) 72 Page - STMicroelectronics |
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72 / 190 page  Functional details BlueNRG-2 72/190 DocID030675 Rev 2 Required bit rate (bps) Programmed divisor Generated bit rate (bps) Error (%) Integer (DIVINT) Fraction (DIVFRAC) 2 400 833 (16’h0341) 21 (6’h15) 2 400 0 1 200 1666 (16’h0682) 43 (6’h2B) 1 199 -0.083 300 6666 (16’h1A0A) 43 (6’h2B) 299 -0.333 110 18181 (16’h4705) 52 (6’h34) 110 0 3.9.2.3 Hardware flow control The hardware flow controls feature is fully selectable through RTSEN and CTSEN in UARTCR register, and allows to control the serial data flow by using the UART_RTS output and UART_CTS input signals. Figure 14: Hardware flow control between two similar devices When the RTS flow control is enabled, the UART_RTS signal is asserted until the receive FIFO is filled up to the programmed watermark level. When the CTS flow control is enabled, the transmitter can only transmit data when the UART_CTS signal is asserted. Table 74: Control bits to enable and disable hardware flow control CTSEN RTSEN Function 0b 0b Both RTS and CTS flow control disabled. 0b 1b Only RTS flow control enabled. 1b 0b Only CTS flow control enabled. 1b 1b Both RTS and CTS flow control enabled. The RTS flow control logic is linked to the programmable receive FIFO watermark levels. When RTS flow control is enabled, the UART_RTS is asserted until the receive FIFO is |
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