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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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BLUENRG-2 датащи(PDF) 27 Page - STMicroelectronics |
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BLUENRG-2 датащи(HTML) 27 Page - STMicroelectronics |
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27 / 190 page  BlueNRG-2 Functional details DocID030675 Rev 2 27/190 Address offset Name RW Reset Description 0x20 CLOCK_EN RW 0x0003FFFF Enable or gates the APB clock of the peripherals. Refer to the detailed description below. 0x24 DMA_CONFIG RW 0x00000000 DMA config. Refer to the detailed description below. 0x28 JTAG_IDCODE R 0x0200A041 BlueNRG-2 JTAG IDCODE. Table 15: CKGEN_SOC - CONTROL register description: address offset CKGEN_SOC_BASE_ADDR+0x00 Bit Field name Reset RW Description 9:0 RESERVED 0x3F0 R RESERVED 13:10 UART_CKDIV 0x0 RW UART baud rate clock setting from 1 to 16 MHz according to the formula 16 / (n + 1) MHz. 31:14 RESERVED 0x007E8 R RESERVED Table 16: CKGEN_SOC - REASON_RST register description: address offset CKGEN_SOC_BASE_ADDR+0x08 Bit Field name Reset RW Description 0 RESERVED 0x0 R RESERVED 1 SYSREQ 0x0 R Reset caused by Cortex-M0 debug asserting SYSRESETREQ 2 WDG 0x0 R Reset caused by assertion of watchdog Reset 3 LOCKUP 0x0 R Reset caused by Cortex-M0 asserting LOCKUP signal 31:4 RESERVED 0x0 R RESERVED Table 17: CKGEN_SOC - DIE_ID register description: address offset CKGEN_SOC_BASE_ADDR+0x1C Bit Field name Reset RW Description 3:0 REV 0x0 R Cut revision 7:4 VERSION 0x0 R Cut version 11:8 PRODUCT 0x01 R Product 31:12 RESERVED 0x0 R RESERVED Table 18: CKGEN_SOC - CLOCK_EN register description: address offset CKGEN_SOC_BASE_ADDR+0x20 Bit Field name Reset RW Description 0 GPIO 0x1 RW GPIO clock 1 NVM 0x1 RW Flash controller clock 2 SYSCTRL 0x1 RW System controller clock |
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