BLUENRG-2 datasheet(96/190 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-2

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DocID030675 Rev 2

Table 102: I2C - TFR register description: address offset I2CX_BASE_ADDR+0x10

Bit

Field name

Reset

Description

7:0

TDATA

0x0

Transmission data. TDATA contains the payload related to a

master write or read-from-slave operation to be written in the Tx

FIFO. TDATA(0) is the first LSB bit transmitted over the I²C line.

In case of master write operation, the Tx FIFO shall be

preloaded otherwise the I²C controller cannot start the

operation until data are available.

In case of read-from-slave operation, when the slave is

addressed, the interrupt RISR:RFSR bit is asserted and the

CPU shall download the data in the FIFO. If the FIFO is empty

and the I²C master is still requiring data, a new request

(RISR:RFSE interrupt bit) is asserted to require additional data

to the CPU. The slave controller stretches the I²C clock line

when no data are available for transmission. Since the Tx FIFO

could contain some pending data related to the previous

transfer (the transfer length may be unknown to the slave

controller), the Tx FIFO is self-flushed before asserting the

I2C_RISR:RFSR bit. Upon completion of the read-from-slave

operation the interrupt bit I2C_RISR:STD is asserted and the

related status of the operation is stored in the I2C_SR register.

In CPU mode, the FIFO management shall be based on the

assertion of the interrupt bit RISR:TXFNE, related to the nearly-

empty threshold.

In DMA mode, the single/burst requests are automatically

executed based on the number of entries available in the TX

FIFO and the related destination burst size programmed in the

I2C_DMAR:DBSIZE_TX register field. The DMA requests are

terminated at the end of the I²C read operation

(notacknowledge received by the master) by a dummy last

single/burst request.

31:8

RESERVED

0x0

RESERVED

Table 103: I2C - SR register description: address offset I2CX_BASE_ADDR+0x14

Bit

Field name

Reset

Description

1:0

0x0

Operation:

00b: MW: master write operation.

01b: MR: master read operation.

10b: WTS: write-to-slave operation.

11b: RFS: read-from-slave operation.

3:2

STATUS

0x0

Controller status. Valid for the operations MW, MR, WTS RFS:

00b: NOP: No operation is in progress.

01b: ON_GOING: An operation is ongoing.

10b: OK: The operation (OP field) has been completed

successfully.

11b: ABORT: The operation (OP field) has been aborted due

to the occurrence of the event described in the CAUSE field.

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