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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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BLUENRG-2 датащи(PDF) 29 Page - STMicroelectronics |
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BLUENRG-2 датащи(HTML) 29 Page - STMicroelectronics |
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29 / 190 page  BlueNRG-2 Functional details DocID030675 Rev 2 29/190 Only one DMA channel for the ADC should be selected at time. Hardware does not prevent selecting more than one DMA channel for ADC. Table 20: CKGEN_SOC - JTAG_IDCODE register description: address offset CKGEN_SOC_BASE_ADDR+0x28 Bit Field name Reset RW Description 0 RESERVED 0x1 R RESERVED 11:1 MANUF_ID 0x020 R Manufacturer ID 27:12 PART_NUMBER 0x200A R Part number 31:28 VERSION_NUM 0x0 R Version CKGEN_BLE peripheral base address (CKGEN_BLE_BASE_ADDR) 0x48100000. Table 21: CKGEN_BLE registers Address offset Name RW Reset Description 0x08 REASON_RST R 0x00000005 Indicates the Reset reason from BLE. Refer to the detailed description below. 0x0C CLK32K_COUNT RW 0x0000000F Counter of 32 kHz clock. Refer to the detailed description below. 0x10 CLK32K_PERIOD R 0x00000000 Period of 32 kHz clock. Refer to the detailed description below. 0x14 CLK32K_FREQ R 0x00000000 Measurement of frequency of 32 kHz clock. Refer to the detailed description below. 0x18 CLK32K_IT RW 0x00000000 Interrupt event for 32 kHz clock measurement. Refer to the detailed description below. Table 22: CKGEN_BLE - REASON_RST register description: address offset CKGEN_BLE_BASE_ADDR+0x08 Bit Field name Reset RW Description 0 RESERVED 0x1 R RESERVED 1 BOR 0x0 R Reset from BOR 2 POR 0x1 R Reset from POR 3 WKP_IO9 0x0 R Wakeup from external IO9 4 WKP_IO10 0x0 R Wakeup from external IO10 5 WKP_IO11 0x0 R Wakeup from external IO11 6 WKP_IO12 0x0 R Wakeup from external IO12 7 WKP_IO13 0x0 R Wakeup from external IO13 8 WKP_BLUE 0x0 R Wakeup coms from the timer 1 expiration in the wakeup control block of the BLE radio |
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