BLUENRG-2 datasheet(57/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

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be burst-loaded or emptied by the system processor or by the DMA, from one to eight

words per transfer. Each 32-bit word from the system fills one entry in FIFO.

The SPI includes a programmable bitrate clock divider and prescaler to generate the serial

output clock signal from the SPI_CLK pin.

3.8.2.1

SPI clock phase and clock polarity

The SPH control bit selects the clock edge that captures data and allows it to change state.

It has the most impact on the first bit transmitted by either allowing or not allowing a clock

transition before the first data capture edge. The SPO bit selects the clock polarity (low or

high) of the clock signal. SPH in conjunction with the SPO bit allow four possible timing

variations listed in the following table.

Table 52: SPI clock phase and clock polarity

SPH

SPO

Timing description

The clock signal is stopped to low inactive level between transfers. The first rising

edge occurs in the middle of the first data bit (with delay). The SPI transmits data one-

half cycle ahead of the rising edge of clock signal and receives data on the rising edge

of clock signal. In case of multi byte transmission, the CS line must be pulsed HIGH

between each data word transfer.

The clock signal is stopped to high inactive level between transfers. The first falling

edge occurs in the middle of the first data bit (with delay). The SPI transmits data one-

half cycle ahead of the falling edge of clock signal and receives data on the falling

edge of clock signal. In case of multi byte transmission, the CS line must be pulsed

HIGH between each data word transfer.

The clock signal is stopped to low inactive level between transfers. The first rising

edge occurs at the start of the first data bit (no delay). The SPI transmits data on the

rising edge of clock signal and receives data on the failing edge of clock signal.

The clock signal is stopped to high inactive level between transfers. The first falling

edge occurs at the start of the first data bit (no delay). The SPI transmits data on the

falling edge of clock signal and receives data on the rising edge of clock signal.

3.8.2.2

Procedure for enabling SPI

The SPI initialization procedure is the following (assuming clocks already enabled):

Clear the SSE bit in the CR1 register. This step is not required after a hardware or

software Reset of the BlueNRG1.

Empty the receive FIFO. This step is not required after a hardware or software Reset

of the device BlueNRG1.

Program IO_MODE to route SPI port signals on those GPIOs. See Section GPIO

operating modes.

Program the SPI clock prescaler register (CPSR), then program the configuration

registers CR0 and CR1.

The transmit FIFO can optionally be filled before enabling the SPI.

Set the SSE bit to enable SPI operation.

The transmit FIFO and the receive FIFO are not cleared when the SSE bit is

cleared.

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