BLUENRG-2 datasheet(125/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

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In this mode, the timer toggles the TnA output upon underflow which is connected to PWMx

pin of the BlueNRG1. This generates a clock signal on TnA with the width and duty cycle

controlled by the values stored in the TnCRB and TnCRB registers.

This is a "processor-independent" PWM clock because once the timer is set up, no more

interaction is required from the software and the CPU in order to generate the PWM signal.

The timer can generate separate interrupts upon reload from TnCRB and TnCRB. The

TnAPND or TnBPND flags, which are set by the hardware upon occurrence of a timer

reload, indicate which interrupt has occurred.

In this mode of operation, Timer/Counter 2 can be used as a simple system timer or an

external-event counter. Counter TnCNT2 counts down with the clock selected by the

Timer/Counter 2 clock selector, and can be configured to generate an interrupt upon

underflow if enabled by the TnDIEN bit.

The interrupts can be enabled or disabled by software.

3.13.2.2

MFT mode 1a: PWM pulse-train mode

Mode1a is used to output a PWM signal thanks to Timer/Counter 1 as for Mode1 but only

in a time window defined by the Timer/Counter2. Indeed, the Timer/Counter2 is used to

specify the number of pulses to output on the IO. The Mode1a corresponds to the Mode1

selected in the TnMDSEL field of TnMCTRL register with in addition the TnPTEN bit set in

the TnMCTRL register. In Mode1a, the Timer/Counter 1 (TnCNT1) will alternatively be

reloaded by TnCRB and TnCRB registers after starting from TnCT1 as for Mode1 and

toggle the TnA output of the MFT connected to PWMx IO each time an underflow occurs.

In parallel, a trigger pulse is sent to Timer/Counter 2 (TnCNT2), decrementing it by one. If

Timer/Counter 2 (TnCNT2) has reached the underflow condition and the end-of-pulse

condition is detected by the trigger logic as well, the clock of Timer/Counter 1 (TnCNT1) is

disabled immediately.

The figure below shows the block diagram related to the MFT mode 1a.

Figure 17: MFT mode 1a block diagram

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