BLUENRG-2 datasheet(75/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

DocID030675 Rev 2

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It is assumed that software flow control is turned off when this feature is used. The

received status (i.e. parity, framing and break error) of special characters does not

have to be valid for these characters to be accepted as valid matches.

3.9.2.5

UART interrupts

There are six individual maskable interrupt sources generated by the UART (single

interrupt signal that drives the NVIC):



TX FIFO empty interrupt



Xoff/ special character interrupt



Receive interrupt



Transmit interrupt



Timeout interrupt



Error interrupt

The user can enable or disable the individual interrupt sources by changing the mask bits

in the UART_IMSC register. Setting the appropriate mask bit to 1b enables the interrupt.

The status of the individual interrupt sources can be read from the UART_RIS register (raw

interrupt status) or from the UART_MIS register (masked interrupt status).

3.9.2.6

TX FIFO empty interrupt

The TX FIFO empty interrupt is asserted whenever the BUSY status bit goes low to

indicate that all DATA has been transmitted. This BUSY bit remains set until the complete

byte, including all the stop bits, has been sent from the shift register. So, the new TX FIFO

empty interrupt will be asserted when the transmit FIFO and the transmit shift register are

empty.

3.9.2.7

Xoff/ special character interrupt

The Xoff/special character interrupt is asserted whenever an Xoff condition is detected by

the receiver (incoming data matches with the programmable Xoff values), or when a

special character detection was performed (incoming data matches with the Xoff2 and

SPECHAR bit set).

3.9.2.8

Receive interrupt

The receive interrupt is asserted HIGH when one of the following conditions occurs:



If the FIFOs are enabled and the number of characters received reaches the

programmed trigger watermark level. The receive interrupt is cleared by reading data

from the receive FIFO until it becomes less than the programmed watermark level, or

by clearing the interrupt by writing a 1b to the corresponding bit in the UART_ICR



If the FIFOs are disabled (have a depth of one location) and there is a data present in

the receiver single location. It is cleared by performing a single read.

3.9.2.9

Transmit interrupt

The transmit interrupt is asserted HIGH when one of the following conditions occurs:



If the FIFOs are enabled and the number of characters in the transmit FIFO is less

than the programmed watermark level. It is cleared by performing writes to the

transmit FIFO until it holds more characters than the programmed watermark level, or

by clearing the interrupt by software.

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